e200z1 Core (Z1)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-11
Preliminary
10.3.2
e200-Specific Special Purpose Registers
The Power Architecture Book E architecture allows implementation-specific special purpose registers.
Those incorporated in the e200 core are as follows:
10.3.2.1
User-Level Registers
The user-level registers can be accessed by all software with either user or supervisor privileges. They
include the following:
•
The L1 Cache Configuration register (L1CFG0). This read-only register allows software to query
the configuration of the L1 Cache. For the e200z1, this register returns all zeros indicating no cache
is present.
10.3.2.2
Supervisor-level registers
The following supervisor-level registers are defined in e200 in addition to the Power Architecture Book E
registers described above:
•
Configuration Registers
— Hardware implementation-dependent register 0 (HID0). This register controls various
processor and system functions.
— Hardware implementation-dependent register 1 (HID1). This register controls various
processor and system functions.
•
Exception Handling and Control Registers
— Machine Check Syndrome register (MCSR). This register provides a syndrome to differentiate
between the different kinds of conditions which can generate a Machine Check.
— Debug Save/Restore register 0 (DSRR0). When enabled, the DSRR0 register is used to save
the address of the instruction at which execution continues when
rfdi
or
se_rfdi
executes at the
end of a debug interrupt handler routine.
— Debug Save/Restore register 1 (DSRR1). When enabled, the DSRR1 register is used to save
machine status on debug interrupts and to restore machine status when
rfdi
or
se_rfdi
executes.
•
Debug Facility Registers
— Debug Control Register 3 (DBCR3)—This register provides control for debug functions not
described in Power Architecture Book E architecture.
— Debug Counter Register (DBCNT)—This register provides counter capability for debug
functions.
•
L1 Cache Configuration Register (L1CFG0) is a read-only register that allows software to query
the configuration of the L1 Cache. For the e200z1, this register returns all zeros.
•
MMU Configuration Register (MMUCFG) is a read-only register that allows software to query the
configuration of the MMU.
•
Memory Management Registers
— MMU Assist (MAS0-MAS4, MAS6) registers. These registers provide the interface to the
e200 core from the Memory Management Unit.
