MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
15-1
Preliminary
Chapter 15
Crossbar Switch (XBAR)
15.1
Introduction
The multi-port crossbar switch (XBAR) implements a hardware interconnection matrix supporting two
simultaneous connections between six master ports and two slave ports. One slave port is used to access
the system RAM. The other slave port is shared by the secondary flash port (port 1), the EBI, and the AIPS.
The XBAR supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports.
The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible
for both slave ports to be in use at the same time as a result of independent master requests. If a slave port
is simultaneously requested by more than one master port, arbitration logic will select the appropriate
master and grant it ownership of the slave port. By default, requesting masters will be treated with
round-robin priority and will be granted access to a slave port if it is the current higher priority master or
when the current higher priority master has completed its operation. If operating with fixed-priority
arbitration, all other masters requesting that slave port will be stalled until the current higher priority
master completes its transactions. The XBAR can be configured to use fixed priority arbitration by
clearing the MCM_MUDCR[PRI] bit.
lists the master IDs for each of the possible bus masters on MPC5510.
15.1.1
Block Diagram
A simplified block diagram of the XBAR illustrates the functionality and interdependence of major blocks
(see
Table 15-1. Master IDs
Master
Master ID XBAR port
e200z1 data
0
m4
e200z1 instr
m0
e200z0
1
m5
eDMA
2
m1
FlexRay
3
m2
EBI
4
m3
Nexus 2+ (e200z1)
8
—
Nexus 2+ (e200z0)
9
—
