Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
16-8
Freescale Semiconductor
Preliminary
16.2.2.5
ECC Registers
There are a number of registers for the sole purpose of reporting and logging of memory failures. This
section describes those registers.
16.2.2.5.1
ECC Configuration Register (ECR)
The ECC configuration register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches that
are discarded due to a change-of-flow operation and buffered operand writes. The ECC reporting logic in
the MCM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the MCM captures specific information (memory address, attributes
and data, bus master number, etc.) that may be useful for subsequent failure analysis.
for the ECC configuration register definition.
Offset:
MCM_BAS 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PRI
W
Reset
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-4. Miscellaneous User-Defined Control Register (MUDCR)
Table 16-5. MUDCR Field Descriptions
Field
Description
PRI
AXBS-lite arbitration priority scheme.
0 Fixed priority arbitration.
1 Round Robin priority arbitration.
bits 1–31 Reserved.
Note: These bits can be read and written; however, writing has no effect other than to set or clear the bits.
Reading returns the values written to the bits.
