Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
16-16
Freescale Semiconductor
Preliminary
in the RAM causes the address, attributes, and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT, and REDR registers and also the appropriate flag (RNCE) in the ECC status register
to be asserted.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC attributes register definition.
16.2.2.5.11
RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the RAM memory. Depending on the state of the ECC configuration register, an ECC event in the RAM
causes the address, attributes, and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT, and REDR registers and also the appropriate flag (RNCE) in the ECC status register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register is read-only; any attempted write is ignored. See
for the RAM
ECC data register definition.
Offset: MCM_BAS 0x0067
Access: User read only
0
1
2
3
4
5
6
7
R
Write
Size
Protection
W
Reset
–
–
–
–
–
–
–
–
Figure 16-14. RAM ECC Attributes (REAT) Register
Table 16-15. REAT Field Descriptions
Field
Description
Write
0 Read access
1 Write access
Size
000 8-bit access
001 16-bit access
010 32-bit access
011 64-bit access
1xx Reserved
Protection Cache:
0xxx Non-cacheable
1xxx Cacheable
Buffer:
x0xx Non-bufferable
x1xx Bufferable
Mode:
xx0x User mode
xx1x Supervisor mode
Type:
xxx0 I-Fetch
xxx1 Data
