Memory Protection Unit (MPU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
17-9
Preliminary
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
•
Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
•
Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
•
Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
The evaluation logic defines the processor access type based on multiple AHB signals: read or write as
specified by the
hwrite
signal and the low-order two bits of
hprot[1:0]
,
which identify a data reference
versus an instruction fetch and the operating mode (supervisor, user) of the requesting processor.
For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses
hwrite
to
determine if the access is a read or write. The
hprot[1:0]
signal is ignored for these masters.
Writes to this word clear the region descriptor’s valid bit. Because it is also expected that system software
may adjust only the access controls within a region descriptor (MPU_RGD
n
.Word2) as different tasks
execute, an alternate programming view of this 32-bit entity is provided. If only the access controls are
being updated, this operation should be performed by writing to MPU_RGDAAC
n
(alternate access
control
n
) as stores to these locations do not affect the descriptor’s valid bit.
Offset: MP 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
M4RE M4WE M3PE
M3SM
M3UM
M2PE M2SM
W
r
w
x
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
M2SM
M2UM
M1PE
M1SM
M1UM
M0PE
M0SM
M0UM
W
r
w
x
r
w
x
r
w
x
Reset
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: Refer to
to see the Master ID assignments.
Figure 17-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
Table 17-7. MPU_RGDn.Word2 Field Descriptions
Field
Description
bits 0–5
Reserved.
Note: These bits must never be set.
M4RE
Bus Master ID 4 Read Enable. If set, this flag allows bus master ID 4 to perform read operations. If cleared, any
attempted read by bus master ID 4 terminates with an access error and the read is not performed.
Note: Bus Master 4 (EBI) is available for Factory Test only.
