Memory Protection Unit (MPU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
17-14
Freescale Semiconductor
Preliminary
17.4
Functional Description
In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss
the operation of the access evaluation macro as well as the handling of error-terminated AHB bus cycles.
17.4.1
Access Evaluation Macro
As discussed, the basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in
evaluation macro inputs the AHB system bus address phase signals (AHB_ap) and the contents of a region
descriptor (RGD
n
) and performs two major functions: region hit determination (
hit_b
) and detection of
an access protection violation (
error
).
Figure 17-10. MPU Access Evaluation Macro
is not a schematic of the actual access evaluation macro, but a generalized block diagram
showing the major functions included in this logic block.
M0SM
Bus Master 0 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master 0 when
operating in supervisor mode. The M0SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M0UM for user mode
M0UM
Bus Master 0 User Mode Access Control. This 3-bit field defines the access controls for bus master 0 when operating
in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be
terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Table 17-9. MPU_RGDAACn Field Descriptions (continued)
Field
Description
hit_b
start
end
error
>
>
RGDn
AHB_ap
hit & error
hit_b | error
>=
<=
r,w,x
