Memory Protection Unit (MPU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
17-16
Freescale Semiconductor
Preliminary
The resulting boolean equation for the processor protection violations is:
cpu_protection_violation
= ~hwrite & ~hprot[0] & ~eff_rgdn[x]
// ifetch & no x
| ~hwrite & hprot[0] & ~eff_rgdn[r]
// data_read & no r
| hwrite & ~eff_rgdn[w]
// data_write & no w
The resulting boolean equation for the non-processor protection violations is:
protection_violation
= ~hwrite & ~eff_rgdn[r]
// data_read & no r
| hwrite & ~eff_rgdn[w]
// data_write & no w
, the output of the protection violation logic is the
error
signal, that is,
error = protection_violation.
The access evaluation macro then uses the
hit_b
and
error
signals to form two outputs. The combined
(
hit_b | error
) signal is used to signal the current access is not allowed and (
~hit_b & error
) is used as
the input to MPU_EDR
n
(error detail register) in the event of an error.
17.4.2
Putting It All Together and AHB Error Terminations
For each AHB slave port being monitored, the MPU performs a reduction-AND of all the individual
(
hit_b | error
) terms from each access evaluation macro. This expression then terminates the bus cycle
with an error and reports a protection error for three conditions:
1. If the access does not hit in any region descriptor, a protection error is reported.
2. If the access hits in a single region descriptor and that region signals a protection violation, a
protection error is reported.
3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then
a protection error is reported.
The third condition reflects that priority is given to permission granting over access denying for
overlapping regions as this approach provides more flexibility to system software in region descriptor
assignments. For an example of the use of overlapping region descriptors, see
When the MPU causes a termination error to occur, the effect on the system depends on the bus master
requesting the access. If the error was caused by a core access, a machine check is taken. If the error was
caused by an eDMA access, an eDMA source or destination error occurs in the eDMA controller, which
can be enabled to provide an interrupt request through the INTC. If the error was caused by a FlexRay
access, a controller host interface (CHI) illegal system memory access error occurs in the FlexRay
controller, which can be enabled to provide an interrupt request to the INTC.
17.5
Initialization Information
The reset state of MPU_CESR[VLD] disables the entire module. While the MPU is disabled, all accesses
from all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The power
dissipation of each access evaluation macro is minimized when the associated region descriptor is marked
as invalid or when MPU_CESR[VLD] = 0.
