Semaphores
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
18-3
Preliminary
if gate = 0b01, then state = locked by e200z1 (master ID = 0)
if gate = 0b10, then state = locked by e200z0 (master ID = 1)
– Uses the bus master ID number as a reference attribute plus the specified data patterns to
validate all write operations
– After it is locked, the gate must be unlocked by a write of zeroes from the locking processor
— Optionally enabled interrupt notification after a failed lock write provides a mechanism to
indicate the gate is unlocked
— Secure reset mechanisms are supported to clear the contents of individual semaphore gates or
notification logic, and clear_all capability
NOTE
Semaphore gates that are locked upon entry into a low-power sleep mode
will be cleared by the internal reset generated upon exiting sleep mode.
Low-power stop modes have no effect on the state of the semaphore gate.
18.1.3
Modes of Operation
The semaphores module does not support any special modes of operation.
18.2
Signal Description
The semaphores module does not include any external signals.
18.3
Memory Map and Registers
This section provides a detailed description of all semaphores registers.
18.3.1
Module Memory Map
The semaphores programming model map is shown in
. The address of each register is given as
an offset to the semaphore base address. Registers are listed in address order, identified by complete name
and mnemonic, and list the type of accesses allowed.
Table 18-1. Semaphores Memory Map
Offset from
SEMA4_BASE
(0xFFF1_0000)
Register
Access
Reset
Value
Section/
Page
0x0000
SEMA4_Gate00 — Semaphores gate 0
R/W
0x00
0x0001
SEMA4_Gate01 — Semaphores gate 1
R/W
0x00
0x0002
SEMA4_Gate02 — Semaphores gate 2
R/W
0x00
0x0003
SEMA4_Gate03 — Semaphores gate 3
R/W
0x00
0x0004
SEMA4_Gate04 — Semaphores gate 4
R/W
0x00
0x0005
SEMA4_Gate05 — Semaphores gate 5
R/W
0x00
