Semaphores
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
18-11
Preliminary
for it means that a processor can both read a location
and
set it to the locked value in the same bus
operation, preventing any other processor from reading or writing memory.” [Hennessy/Patterson,
Computer Architecture: A Quantitative Approach
, ppg. 471-472]
The classic text continues with a description of the steps required to lock/unlock a variable using an atomic
swap instruction.
“Assume that 0 means unlocked and 1 means locked. A processor first reads the lock variable to
test its state. A processor keeps reading and testing until the value indicates that the lock is
unlocked. The processor then races against all other processes that were similarly “spin waiting”
to see who can lock the variable first. All processes use a swap instruction that reads the old value
and stores a 1 into the lock variable. The single winner will see the 0, and the losers will see a 1
that was placed there by the winner. (The losers will continue to set the variable to the locked value,
but that doesn’t matter.) The winning processor executes the code after the lock and then stores a
0 into the lock when it exits, starting the race all over again. Testing the old value and then setting
to a new value is why the atomic swap instruction is called
test and set
in some instruction sets.”
[Hennessy/Patterson,
Computer Architecture: A Quantitative Approach
, ppg. 472-473]
The sole drawback to a hardware-based semaphore module is the limited number of semaphores versus
the infinite number that can be supported with PowerPC reservation instructions.
18.4.1
Semaphore Usage
Example 1: Inter-processor communication done with software interrupts and semaphores...
•
The Z0 uses software interrupts to tell the Z1 that new data is available, or the Z1 does the same to
tell the Z0 that there is new data available for transmission.
•
Because only eight software interrupts are available, the user may need RAM locations or
general-purpose registers in the SIU to refine the meaning of the software interrupt.
•
Messages are passed between cores in a defined section of system RAM.
•
Before a core updates a message, it must check the associated semaphore to see if the other core is
in the process of updating the same message. If the RAM not being updated, then the semaphore
must first be locked, then the message can be updated. A software interrupt can be sent to the other
core and the semaphore can be unlocked. If the RAM is being updated, the CPU must wait for the
other core to unlock the semaphore before proceeding with update.
•
Using the same memory location for bidirectional communication might be difficult, so two
one-way message areas might work better.
— For example, if both cores want to update the same location, then the following sequence may
occur.
1. The Z0 locks the semaphore, updates the memory, unlocks the semaphore, and generates a
software interrupt to the Z1.
2. Before the Z1 takes the software interrupt request, it finds the semaphore to be unlocked, so
it writes new data to the memory.
3. The Z1 software interrupt ISR reads the data sent to the Z0, not the data sent from the Z0,
and performs an incorrect operation.
— Semaphores do not prevent this situation from occurring.
