MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
19-1
Preliminary
Chapter 19
IEEE 1149.1 Test Access Port Controller (JTAGC)
19.1
Introduction
The JTAGC provides the means to test chip functionality and connectivity and controls access to the debug
features of the device, while remaining transparent to system logic when the JTAGC is not in test mode.
Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard.
Instructions can be executed that allow the test access port (TAP) to be shared with other modules on the
MCU. All data input to and output from the JTAGC is communicated in serial format.
19.1.1
Block Diagram
A simplified block diagram of the JTAGC illustrates the functionality and interdependence of major blocks
(see
). The JTAG port of the device consists of four inputs and one output. These pins include
JTAG compliance select (JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS),
and test clock input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard
and are shared with the NDI through the test access port (TAP) interface.
Figure 19-1. JTAGC Block Diagram
TCK
TMS
TDI
Test access port (TAP)
TDO
32-bit device identification register
Boundary scan register
.
.
controller
1-bit bypass register
.
5-bit TAP instruction decoder
5-bit TAP instruction register
.
.
.
JCOMP
Power-on
reset
