IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
19-2
Freescale Semiconductor
Preliminary
Figure 19-2. JTAG/Nexus Daisy Chain of the MPC5510 e200z1 and e200z0 Cores
19.1.2
Features
The JTAGC is compliant with the IEEE 1149.1-2001 standard and has these major features:
•
IEEE 1149.1-2001 test access port (TAP) interface.
•
A JCOMP input that provides the ability to share the TAP.
•
A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions, as well as
several public and private MCU specific instructions.
•
Three test data registers: a bypass register, a boundary scan register, and a device identification
register. The size of the boundary scan register is 276 bits.
•
A TAP controller state machine that controls the operation of the data registers, instruction register,
and associated circuitry.
19.1.3
Modes of Operation
The JTAGC uses JCOMP and a power-on reset indication as its primary reset signals. Several IEEE
1149.1-2001 defined test modes are supported, as well as a bypass mode.
TDO
e200z1 OnCE TAP
TDI
TDI
TDO
TDO
TDI
e200z0 OnCE TAP
NPC/JTAGC
ACCESS_AUX_TAP_OnCE
ACCESS_AUX_TAP_MULTI
ACCESS_AUX_TAP_Z0
Multi-core access
Single-core access
TMS and JCOMP are not shown for clarity.
NPC TAP also not shown for clarity.
