IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
19-6
Freescale Semiconductor
Preliminary
19.4.2
IEEE 1149.1-2001 (JTAG) Test Access Port
The JTAGC uses the IEEE 1149.1-2001 TAP for accessing registers. This port can be shared with other
TAP controllers on the MCU. Ownership of the port is determined by the value of the JCOMP signal and
the currently loaded instruction. For more detail on TAP sharing via JTAGC instructions refer to
Section 19.4.4.2, “ACCESS_AUX_TAP_x Instructions
Data is shifted between TDI and TDO though the selected register starting with the least significant bit, as
illustrated in
. This applies for the instruction register, test data registers, and the bypass
register.
Figure 19-5. Shifting Data Through a Register
19.4.3
TAP Controller State Machine
The TAP controller is a synchronous state machine that interprets the sequence of logical values on the
TMS pin.
shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCK signal. As
shows, holding TMS at logic 1
while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the
test-logic-reset state.
Selected Register
msb
lsb
TDI
TDO
