IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
19-8
Freescale Semiconductor
Preliminary
19.4.3.1
Enabling the TAP Controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
19.4.3.2
Selecting an IEEE 1149.1-2001 Register
Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path is used to read or write the register data by shifting in the data (lsb first) during
the shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting may be terminated after the required number of bits have been
acquired.
19.4.4
JTAGC Instructions
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in
an overview of each instruction, refer to the IEEE 1149.1-2001 standard for more details
Table 19-2. JTAG Instructions
Instruction
Code[4:0]
Instruction Summary
IDCODE
00001
Selects device identification register for shift
SAMPLE/PRELOAD
00010
Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
SAMPLE
00011
Selects boundary scan register for shifting and sampling
without disturbing functional operation
EXTEST
00100
Selects boundary scan register while applying preloaded
values to output pins and asserting functional reset
HIGHZ
01001
Selects bypass register while three-stating all output pins and
asserting functional reset
CLAMP
01100
Selects bypass register while applying preloaded values to
output pins and asserting functional reset
ACCESS_AUX_TAP_NPC
10000
Grants the Nexus port controller (NPC) ownership of the TAP
ACCESS_AUX_TAP_ONCE
10001
Grants the Nexus e200z1 core interface ownership of the TAP
ACCESS_AUX_TAP_Z0
11001
Grants the Nexus e200z0 core interface ownership of the TAP
ACCESS_AUX_TAP_MULTI
11100
Daisy chaining the e200z1 and e200z0 cores—allows
instructions to be clocked into both the e200z0 and e200z1
serially.
BYPASS
11111
Selects bypass register for data operations
