IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
19-9
Preliminary
19.4.4.1
BYPASS Instruction
BYPASS selects the bypass register, creating a single-bit shift register path between TDI and TDO.
BYPASS enhances test efficiency by reducing the overall shift path when no test operation of the MCU is
required. This allows more rapid movement of test data to and from other components on a board that are
required to perform test functions. While the BYPASS instruction is active, the system logic operates
normally.
19.4.4.2
ACCESS_AUX_TAP_x Instructions
The ACCESS_AUX_TAP_
x
instructions allow the Nexus modules on the MCU to take control of the TAP.
When this instruction is loaded, control of the TAP pins is transferred to the selected auxiliary TAP
controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any TDO output
from the selected TAP controller is sent back to the JTAGC to be output on the pins. The JTAGC regains
control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was entered. Auxiliary TAP
controllers are held in RUN-TEST/IDLE while they are inactive.
Section 19.5, “e200z0 and e200z1 OnCE Controllers
,” for a block diagram and e200z0 OnCE
controller register descriptions.
19.4.4.3
CLAMP Instruction
CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan
register while the bypass register is selected as the serial path between TDI and TDO. CLAMP enhances
test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an
EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system
reset for the MCU to force a predictable internal state.
19.4.4.4
EXTEST — External Test Instruction
EXTEST selects the boundary scan register as the shift path between TDI and TDO. It allows testing of
off-chip circuitry and board-level interconnections by driving preloaded data contained in the boundary
scan register onto the system output pins. Typically, the preloaded data is loaded into the boundary scan
register using the SAMPLE/PRELOAD instruction before the selection of EXTEST. EXTEST asserts the
internal system reset for the MCU to force a predictable internal state while performing external boundary
scan operations.
Factory Debug Reserved
1
00101, 00110,
01010
Intended for factory debug only
Reserved
2
All Other Codes
Decoded to select bypass register
1
Intended for factory debug, and not customer use
2
Freescale reserves the right to change the decoding of reserved instruction codes in the future
Table 19-2. JTAG Instructions (continued)
Instruction
Code[4:0]
Instruction Summary
