IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
19-11
Preliminary
19.5
e200z0 and e200z1 OnCE Controllers
The e200z0 core OnCE controller supports a complete set of Nexus 1 debug features, as well as providing
access to the configuration registers. A complete discussion of the e200z0 OnCE debug features
is available in the
e200z0 Reference Manual
.
The following sections will describe functionality of the e200z0 OnCE controller; however, the e200z1
OnCE controller operates in the same manner as the e200z0 OnCE controller, and is fully documented in
the
e200z1 Reference Manual
.
NOTE
The register select field in the e200z1 OnCE command register
(OCMD[RS]) does not implement the shared nexus control register (SNC).
19.5.1
e200z0 OnCE Controller Block Diagram
is a block diagram of the e200z0 OnCE block.
Figure 19-7. e200z0 OnCE Block Diagram
19.5.2
e200z0 OnCE Controller Functional Description
The functional description for the e200z0 OnCE controller is the same as for the JTAGC, with the
differences described below.
TCK
e200z0_TMS
TDI
Test Access Port (TAP)
e200z0_TDO
Bypass Register
External Data Register
.
.
Controller
TAP Instruction Register
.
OnCE Mapped Debug Registers
Auxiliary Data Register
.
.
.
e200z0_TRST
(OnCE OCMD)
TDO Mux
Control
{
From
JTAGC
(to JTAGC)
