IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
19-13
Preliminary
19.5.3.2
OnCE Shared Nexus Control Register (SNC)
This register determines which core has ownership of the tracing functionality, which core’s
master ID is used during DMA access, and if the Nexus EVTI debug request is used as a debug
request to either or both cores. This register is only available on the e200z0 core.
000 0011 – 000 1111
Reserved
001 0000
CPU Scan Register (CPUSCR)
001 0001
No Register Selected (Bypass)
001 0010
OnCE Control Register (OCR)
001 0011 – 001 1111
Reserved
010 0000
Instruction Address Compare 1 (IAC1)
010 0001
Instruction Address Compare 2 (IAC2)
010 0010
Instruction Address Compare 3 (IAC3)
010 0011
Instruction Address Compare 4 (IAC4)
010 0100
Data Address Compare 1 (DAC1)
010 0101
Data Address Compare 2 (DAC2)
010 0110 – 010 1111
Reserved
011 0000
Debug Status Register (DBSR)
011 0001
Debug Control Register 0 (DBCR0)
011 0010
Debug Control Register 1 (DBCR1)
011 0011
Debug Control Register 2 (DBCR2)
011 0100 – 101 1111
Reserved (do not access)
110 1111
Shared Nexus Control Register (SNC)
(only available on the e200z0 core)
111 0000 – 111 1001
General Purpose Register Selects [0:9]
111 1010 – 111 1011
Reserved
111 1100
Access
111 1101
LSRL Select
(factory test use only)
111 1110
Enable_OnCE
111 1111
Bypass
Table 19-3. e200z0 OnCE Register Addressing (continued)
RS
Register Selected
