Flash Array and Control
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
22-9
Preliminary
Figure 22-4. PEG Valid Times
22.4.2.1.1
MCR Simultaneous Register Writes
A number of MCR bits are protected against write when another bit or set of bits is in a specific state. These
write locks are covered on a bit by bit basis in
Section 22.4.2.1, “Module Configuration Register (MCR)
The write locks detailed in that section do not consider the effects of trying to write two or more bits
simultaneously. The effects of writing bits simultaneously, which would put the flash module in an illegal
state, are detailed here.
The flash does not allow the user to write bits simultaneously. This is implemented through a priority
mechanism among the bits. The bit changing priorities are detailed in
If the user attempts to write two or more MCR bits simultaneously, only the bit with the highest priority
level will be written. Setting two bits with the same priority level is prevented by existing write locks and
will not put the flash in an illegal state.
For example, setting MCR[STOP] and MCR[PGM] simultaneously results in MCR[STOP] only being set.
Attempting to clear MCR[EHV] while setting MCR[PSUS] will result in MCR[EHV] being cleared, but
MCR[PSUS] will remain unaffected.
22.4.2.2
Low-/Mid-Address Space Block Locking Register
The low- and mid-address block locking register provides a means to protect blocks from being modified.
These bits along with bits in the secondary locking register (SLL), determine if the block is locked from
program or erase. An “OR” of LML and SLL determine the final lock status. See
“Secondary Low-/Mid-Address Space Block Locking Register (SLL)
,” for more information on SLL.
Table 22-4. MCR Bit Set/Clear Priority Levels
Priority Level
MCR Bits
1
STOP
2
ERS
3
PGM
4
EHV
5
ESUS, PSUS
MCR[PGM/ERS]
MCR[EHV]
MCR[DONE]
MCR[PEG]
PEG
Valid
PEG
Valid
PEG
Valid
Abort
Program/Erase
