Flash Array and Control
MPC5510 Microcontroller Family Reference Manual, Rev. 1
22-18
Freescale Semiconductor
Preliminary
22.5
Functional Description
22.5.1
Flash
User Mode
In user mode the flash module can be read and written (register writes and interlock writes), programmed
or erased. The following sub-sections define all actions that can be performed in user mode.
22.5.2
Flash Read and Write
The default state of the flash module is read. The main and shadow address space can be read only in the
read state. The module configuration register (MCR) is always available for read. The flash module enters
the read state on reset. The flash module is in the read state under four sets of conditions:
•
The read state is active when STOP=0 in the MCR (user mode read).
•
The read state is active when PGM=1 or ERS=1 in the MCR and high-voltage operation is ongoing
(read while write).
NOTE
Reads done to the partition(s) being operated on (either erased or
programmed) will result in an error and the RWE bit in the MCR will be set.
•
The read state is active when PGM=1 and PSUS=1 in the MCR (program suspend).
•
The read state is active when ERS=1 and ESUS=1 and PGM=0 in the MCR (erase suspend).
NOTE
FC reads are done through the BIU. In many cases the BIU will do page
buffering to allow sequential reads to be done with higher performance. This
can create a data coherency issue that must be handled with software. Data
coherency can be an issue after a program, erase, or shadow row operations.
In flash user mode, registers can be written. Array can be written to do interlock writes.
PFLIM
PFLASH Prefetch Limit. Controls the prefetch algorithm used by the PFLASH prefetch controller. This field
defines a limit on the maximum number of sequential prefetches which will be attempted between buffer misses.
In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared
by hardware reset.
00 No prefetching or buffering is performed
01 The referenced line is prefetched on a buffer miss, i.e., prefetch on miss
1x the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if
not already present), i.e., prefetch on miss or hit
BFEN
PFLASH Line Read Buffers Enable. Enables or disables line read buffer hits. It is also used to invalidate the
buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers
are successfully filled
Table 22-11. PFCRP0 and PFCRP1 Field Descriptions (continued)
Field
Description
