Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-2
Freescale Semiconductor
Preliminary
Figure 23-1. DSPI Block Diagram
23.1.2
Features
The DSPI supports these SPI features:
•
Full-duplex, synchronous transfers
•
Master and slave mode
•
Buffered operation with separate four-entry TX and RX FIFOs
•
Visibility into the TX and RX FIFOs for ease of debugging
•
FIFO bypass mode for low-latency updates to SPI queues
•
Programmable SPI transfer attributes on a per-frame basis:
— Eight clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays:
– PCS to SCK delay
CMD
DMA and interrupt control
TX FIFO
RX FIFO
TX data
RX data
16
16
Shift register
SOUT
SPI
SPI and DSI baud rate,
delay and transfer
control
CSI
priority
logic
TXSS
DSI
DSPI BIU
16
From eMIOS200
output channels
16
To eMIOS200
input channels
SIU / IMUX
1
SIN
SCK
PCS
[0]
/SS
PCS[4:1]
PCS[5]/PCSS
INTC
eDMA
Peripheral bus
4
16
Host CPU / DMA
update
16
16
16
1
Parallel outputs to the eMIOS200 are not su0pported by SDPI_D.
