Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-21
Preliminary
23.3.2.6
DSPI PUSH TX FIFO Register (DSPI_PUSHR)
The DSPI_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred
to the TX FIFO. See
Section 23.4.3.4, “Transmit First-In First-Out (TX FIFO) Buffering Mechanism
,” for
more information. Write accesses of 8- or 16-bits to the DSPI_PUSHR will transfer 32 bits to the TX FIFO.
NOTE
Only the TXDATA field is used for DSPI slaves.
RFDF_RE
Receive FIFO Drain Request Enable. Enables the RFDF flag in the DSPI_SR to generate a request. The
RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
0 RFDF interrupt requests or DMA requests are disabled
1 RFDF interrupt requests or DMA requests are enabled
RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. Selects between generating a DMA request or an interrupt
request. When the RFDF flag bit in the DSPI_SR is set and the RFDF_RE bit in the DSPI_RSER is set, the
RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
0 Interrupt request will be generated
1 DMA request will be generated
bits 16–31
Reserved.
Offset: DSP 0x0034
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CONT
CTAS
EOQ
CT
CNT
0
0
0
0
PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TXDATA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-7. DSPI PUSH TX FIFO Register (DSPI_PUSHR)
Table 23-6. DSPI_RSER Field Descriptions (continued)
Field
Description
