Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-37
Preliminary
Figure 23-18. DSI Serialization Diagram
23.4.4.4
DSI Deserialization
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPI
x
_DDR. This register
presents the deserialized data as parallel output signal values. The DSPI
x
_DDR is memory mapped to
allow host software to read the deserialized data directly.
shows the DSI deserialization logic.
for more information on the DSPI
x
Section 23.3.2.14, “DSPI DSI Deserialization Data
.”
Figure 23-19. DSI Deserialization Diagram
23.4.4.5
DSI Transfer Initiation Control
Data transfers for a master DSPI in DSI configuration are initiated by a condition. When chaining DSPIs,
the master and all slaves must be configured for the transfer initiation. The transfer initiation conditions
are selected by the CID bit in the DSPI
x
_DSICR.
lists the two transfer initiation conditions.
1
0
DSPI Alternate
Serialization Data Register
SOUT
x
Parallel
DSI Configuration
Register
DSI Transmit
Comparison Register
Clock
Logic
0 1 • • • • • 15
Shift Register
DSI Serialization
Data Register
Control
Logic
SCK
x
Inputs
PCS
x
16
16
16
16
TXSS
Slave Bus Interface
16
SIN
Control
Logic
0 1 • • • • • 15
Shift Register
16
Slave Bus Interface
Parallel
DSI Deserialization
Data Register
Outputs
1
16
1
Parallel outputs not supported by DSPI_D.
