Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-44
Freescale Semiconductor
Preliminary
23.4.6
Buffered SPI Operation
The DSPI can use a FIFO buffering mechanism to transmit and receive commands and data to and from
external devices. The transmit FIFO buffers SPI commands and data to be transferred. The receive FIFO
buffers incoming serial data. Both FIFOs are four entries deep. The TX FIFO stores 32-bit words when the
DSPIs are configured for master mode. The 32-bit words are composed of 16-bit command fields and data
fields up to 16 bits wide. The RX FIFOs store 16-bit words of received data from external devices. When
the DSPI is configured for slave mode, the DSPI ignores the SPI command in the TX FIFO. See the DSPI
block guide for a complete description of the command portion of the TX FIFO.
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through host software. See
for conceptual diagram of the queue data transfer control in the
MCU.
Figure 23-27. DSPI Queue Transfer Control in MPC5510
23.4.7
DSPI Baud Rate and Clock Delay Generation
The SCK
x
frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option of doubling the baud rate.
conceptually how the SCK signal is generated.
Figure 23-28. Communications Clock Prescalers and Scalers
System RAM
DSPI
DMA controller/
TX queue
RX FIFO
TX FIFO
Shift register
Data
Data
Address
RX queue
Data
Data
Address
DMA
control/
host
host
Prescaler
1
Scaler
1+DBR
System clock
SCKx
