Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-54
Freescale Semiconductor
Preliminary
Enabling continuous SCK disables the PCS to SCK delay and the after SCK delay. The delay after transfer
is fixed at one SCK cycle.
shows timing diagram for continuous SCK format with continuous
selection disabled.
Figure 23-37. Continuous SCK Timing Diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPI
x
_DSICR is set, PCS remains
asserted between the transfers when the PCS signal for the next transfer is the same as for the current
transfer.
shows timing diagram for continuous SCK format with continuous selection
enabled.
Figure 23-38. Continuous SCK Timing Diagram (CONT=1)
23.4.10 Peripheral Chip Select Expansion and Deglitching
The DSPI supports up to 64 peripheral chip select signals with the use of an external demultiplexer. Up to
32 peripheral chip select signals can be used if deglitching is desired. The PCSS signal provides the
appropriate timing to enable and disable the demultiplexer for the PCS[0:4] signals.
shows how an external 5-to-32 demultiplexer (decoder) can be connected to the DSPI.
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK.
Master SIN
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1
Transfer 2
