Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-56
Freescale Semiconductor
Preliminary
23.4.11.3 Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI
x
_RSER. See
Section 23.3.2.4, “DSPI Status Register (DSPI_SR)
and
that illustrate when TCF is set.
23.4.11.4 Transmit FIFO Underflow Flag (TFUF)
The Transmit FIFO Underflow Flag indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI blocks operating in slave mode and SPI
configuration. The transmit underflow condition is detected when the TX FIFO of a DSPI operating as a
SPI slave is empty, and a transfer is initiated from an external SPI master.
23.4.11.5 Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
DSPI
x
_RSER is asserted. The RFDF_DIRS bit in the DSPI
x
_RSER selects whether a DMA request or an
interrupt request is generated.
23.4.11.6 Receive FIFO Overflow Flag (RFOF)
The receive FIFO overflow flag indicates that an overflow condition in the RX FIFO has occurred, and
that data may be lost. The receive FIFO overflow flag is asserted when the RX FIFO is full, a new frame
has been received in the shift register, and a transfer is initiated.
23.4.11.7 DMA Requests
The connection of the DSPI DMA request signals to the DMA channel mux is described in
23.4.11.8 Interrupt Requests
The DSPI interrupts on connected as described in
23.4.12 Power Saving Features
The DSPI supports three power-saving strategies:
•
Halt mode
•
Module disable mode—clock gating of non-memory mapped logic
•
Clock gating of slave interface signals and clock to memory-mapped logic
23.4.12.1 Halt Mode
By setting the appropriate bit in the SIU_HLT register, a request is made to shut down all clocks in the
DSPI. If there is no serial transfer in progress, the DSPI immediately asserts an acknowledge signal to the
system, allowing the clocks to be disabled. If a serial transfer is in progress when the request is received,
