Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-57
Preliminary
the DSPI waits until it reaches a frame boundary before it asserts the acknowledge signal to the system.
The status of this acknowledge signal can be determined by reading the SIU_HLTACK register.
While the clocks are shut off, the DSPI memory-mapped logic is not accessible. The states of the interrupt
and DMA request signals cannot be changed while in Halt Mode.
Halt Mode is exited by negating the appropriate bit in the SIU_HLT register.
23.4.12.2 Module Disable Mode
Module disable mode is a module-specific mode that the DSPI can enter to save power. Host software can
initiate the module disable mode by writing a 1 to the MDIS bit in the DSPI
x
_MCR.
In module disable mode, the DSPI is in a dormant state, but the memory mapped registers are still
accessible. Certain read or write operations have a different affect when the DSPI is in the module disable
mode. Reading the RX FIFO pop register will not change the state of the RX FIFO. Likewise, writing to
the TX FIFO push register will not change the state of the TX FIFO. Clearing either of the FIFOs will not
have any affect in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the
DSPI
x
_MCR will not have any affect in the module disable mode. In the module disable mode, all status
bits and register flags in the DSPI will return the correct values when read, but writing to them will have
no affect. Writing to the DSPI
x
_TCR during module disable mode will not have any affect. Interrupt and
DMA request signals cannot be cleared while in the module disable mode.
23.4.12.3 Slave Interface Signal Gating
The DSPI’s module enable signal is used to gate slave interface signals such as address, byte enable,
read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed.
23.5
Initialization/Application Information
23.5.1
How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPI
x
_SR is set.
3. The setting of the EOQF flag will disable both serial transmission, and serial reception of data,
putting the DSPI in the STOPPED state. The TXRXS bit is negated to indicate the STOPPED state.
4. The eDMA will continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the eDMA controller.
