Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-58
Freescale Semiconductor
Preliminary
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPI
x
_SR or by checking RFDF in the DSPI
x
_SR after each read operation of the
DSPI
x
_POPR.
7. Modify DMA descriptor of TX and RX channels for new queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPI
x
_MCR, Flush RX FIFO by writing
a 1 to the CLR_RXF bit in the DSPI
x
_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the DSPI
x
_TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
23.5.2
Baud Rate Settings
shows the baud rate that is generated based on the combination of the baud rate prescaler PBR
and the baud rate scaler BR in the DSPI
x
_CTARs. The values calculated assume a 66 MHz system
frequency.
