Enhanced Serial Communication Interface (eSCI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
24-18
Freescale Semiconductor
Preliminary
24.4.2
Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value, 1 to 8191, written to the SBR bits determines the system clock divider. The SBR
bits are in the eSCI control register 1 (ESCI
x
_CR1). The baud rate clock is synchronized with the system
clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an
acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
•
Integer division of the system clock may not give the exact target frequency.
lists some examples of achieving target baud rates with a system clock frequency of 66 MHz.
Table 24-14. Example of 8-bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1
8
0
0
1
1
7
0
1
1
1
7
1
1
1
The address bit identifies the frame as an address char-
acter. See
Section 24.4.4.6, “Receiver Wakeup
0
1
Table 24-15. Example of 9-Bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1
9
0
0
1
1
8
0
1
1
1
8
1
1
1
The address bit identifies the frame as an address char-
acter. See
Section 24.4.4.6, “Receiver Wakeup
0
1
Table 24-16. Baud Rates (Example: System Clock = 66 MHz)
Value in
SBR
Receiver
clock (Hz)
Transmitter
clock (Hz)
Target baud
rate
Error
(%)
0x0012
3,666,667
229,167
230,400
–0.54
0x0024
1,833,333
114,583
115,200
–0.54
0x0048
916,667
57,292
57,600
–0.54
0x006B
616,822
38,551
38,400
+0.39
0x00D7
306,977
19,186
19,200
–0.07
SCI baud rate
System clock
16
ESCIx_CR1[SBR]
×
-------------------------------------------------------------
=
