Enhanced Serial Communication Interface (eSCI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
24-24
Freescale Semiconductor
Preliminary
24.4.4.1
Receiver Character Length
The eSCI receiver can accommodate 8-bit or 9-bit data characters. The state of the M bit in eSCI control
register 1 (ESCI
x
_CR1) determines the length of data characters. When receiving 9-bit data, bit R8 in the
eSCI data register (ESCI
x
_DR) is the ninth bit (bit 8).
24.4.4.2
Character Reception
During an eSCI reception, the receive shift register shifts a frame in from the RXD input
signal. The eSCI
data register is the buffer (read-only during receive) between the internal data bus and the receive shift
register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
eSCI data register. The receive data register full flag, RDRF, in eSCI status register (ESCI
x
_SR) is then
set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in eSCI control
register 1 (ESCI
x
_CR1) is also set, the RDRF flag generates an RDRF interrupt request.
24.4.4.3
Data Sampling
The receiver uses a sampling clock to sample the RXD input
signal at the 16 times the baud-rate frequency.
This sampling clock is called the RT clock. To adjust for baud rate mismatch, the RT clock (see
) is re-synchronized:
•
After every start bit.
•
After the receiver detects a data bit change from logic 1 to logic 0. This data bit change is detected
when a majority of data samples return a valid logic 1 and a majority of the next data samples return
a valid logic 0. Data samples are taken at RT8, RT9, and RT10, as shown in
To locate the start bit, eSCI data recovery logic performs an asynchronous search for a logic 0 preceded
by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Figure 24-17. Receiver Data Sampling
To verify the start bit and to detect noise, the eSCI data recovery logic takes samples at RT3, RT5, and
RT7.
summarizes the results of the start bit verification samples.
RT clock
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Start bit
qualification
Start bit
verification
Data
sampling
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT3
RT5
RT7
RT9
RT11
RT13 RT15
RT1
RT3
RT2
RT4
RT6
RT8
RT10
RT12 RT14 RT16
RT2
RT4
Reset
RT clock
RT clock
count
RXD input
signal
samples
Start bit
LSB
