Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
25-21
Preliminary
25.3.4.5
Error Counter Register (CANx_ECR)
CANx_ECR has two 8-bit fields reflecting the value of two FlexCAN error counters: the transmit error
counter (TXECTR field) and receive error counter (RXECTR field)
.
The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN module. Both counters are read only except in freeze mode, where they can be written by the
CPU.
Writing to the CANx_ECR while in freeze mode is an indirect operation. The data is first written to an
auxiliary register and then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN responds to any bus state as described in the protocol: transmitting, for example, an ‘error active’
or ‘error passive’ flag, delaying its transmission start time (‘error passive’), and avoiding any influence on
the bus when in the bus off state. The following are the basic rules for FlexCAN bus state transitions:
•
If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the CANx_ESR is updated to reflect the ‘error passive’ state.
•
If the FlexCAN state is ‘error passive,’ and either TXECTR or RXECTR decrements to a value
less than or equal to 127 while the other already satisfies this condition, the FLTCONF field in the
CANx_ESR is updated to reflect the ‘error active’ state.
•
If the value of TXECTR increases to be greater than 255, the FLTCONF field in the CANx_ESR
is updated to reflect the bus off state, and an interrupt may be issued. The value of TXECTR is then
reset to zero.
•
If FlexCAN is in the bus off state, then TXECTR is cascaded together with another internal counter
to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset
to zero and counts in a manner where the internal counter counts 11 such bits and then wraps
around while incrementing the TXECTR. When TXECTR reaches the value of 128, the FLTCONF
field in CANx_ESR is updated to be ‘error active’ and both error counters are reset to zero. At any
instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal
counter resets itself to zero without affecting the TXECTR value.
•
If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ACKERR bit in
CANx_ESR). After the transition to the ‘error passive’ state, the TXECTR does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus off state.
If the RXECTR increases to a value greater than 127, it is not incremented further, even if more errors are
detected while being a receiver. At the next successful message reception, the counter is set to a value
between 119 and 127 to resume to ‘error active’ state.
