Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
25-31
Preliminary
Upon receiving the MB interrupt, the CPU should service the received frame using the following
procedure:
•
Read the control and status word (mandatory – activates an internal lock for this buffer)
•
Read the ID field (optional – needed only if a mask was used)
•
Read the data field
•
Read the free-running timer (optional – releases the internal lock)
Upon reading the control and status word, if the BUSY bit is set in the code field, then the CPU should
defer the access to the MB until this bit is negated. Reading the free-running timer is not mandatory. If not
executed, the MB remains locked, unless the CPU reads the C/S word of another MB. Only a single MB
is locked at a time. The only mandatory CPU read operation is the one on the control and status word to
assure data coherency (see
Section 25.4.5, “Data Coherence
The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the
CANx_IFLAG registers and not by the code field of that MB. Polling the code field does not work because
after a frame was received and the CPU services the MB (by reading the C/S word followed by unlocking
the MB), the code field will not return to EMPTY. It will remain FULL, as explained in
CPU tries to workaround this behavior by writing to the C/S word to force an EMPTY code after reading
the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly
received frame matching the ID of that MB may be lost. In summary:
never do polling by reading directly
the C/S word of the MBs. Instead, read the CANx_IFLAG registers.
The received ID field is always stored in the matching MB, thus the contents of the ID field in an MB may
change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself
if there exists an Rx matching MB, provided the SRX_DIS bit in the CANx_MCR is not asserted. If
SRX_DIS is asserted, FlexCAN will not store frames transmitted by itself in any MB, even if it contains
a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO during
freeze mode (see
”). Upon receiving the frames available interrupt from FIFO,
the CPU should service the received frame using the following procedure:
•
Read the control and status word (optional – needed only if a mask was used for IDE and RTR bits)
•
Read the ID field (optional – needed only if a mask was used)
•
Read the data field
•
Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read the
next FIFO entry)
25.4.4
Matching Process
The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx
MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the
8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the
other MBs are scanned. In the event that the FIFO is full, the matching algorithm will always look for a
matching MB outside the FIFO region.
