Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
25-35
Preliminary
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the array are
programmed with the same ID, and FlexCAN has already received and stored messages into these two
MBs. Suppose now that the CPU decides to read MB number 5 and at the same time another message with
the same ID is arriving. When the CPU reads the control and status word of MB number 5, this MB is
locked. The new message arrives and the matching algorithm finds out that there are no free to receive
MBs, so it decides to override MB number 5. However, this MB is locked, so the new message can not be
written there. It will remain in the SMB waiting for the MB to be unlocked, and only then will be written
to the MB. If the MB is not unlocked in time and yet another new message with the same ID arrives, then
the new message overwrites the one on the SMB and there will be no indication of lost messages either in
the code field of the MB or in the error and status register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the code field is asserted.
If the CPU reads the control and status word and finds out that the BUSY bit is set, it should defer accessing
the MB until the BUSY bit is negated.
NOTE
If the BUSY bit is asserted or if the MB is empty, then reading the control
and status word does not lock the MB.
Deactivation takes precedence over locking. If the CPU deactivates a locked Rx MB, then its lock status
is negated and the MB is marked as invalid for the current matching round. Any pending message on the
SMB will not be transferred anymore to the MB.
25.4.6
Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the CANx_MCR. The reset value of this bit
is zero to maintain software backwards compatibility with previous versions of the module that did not
have the FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first 8
MBs (0x80-0xFF) is now reserved for use of the FIFO engine (see
Section 25.3.3, “Rx FIFO Structure
”).
Management of read and write pointers is done internally by the FIFO engine. The CPU can read the
received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer
structure at the beginning of the memory.
The FIFO can store up to six frames pending service by the CPU. An interrupt is sent to the CPU when
new frames are available in the FIFO. Upon receiving the interrupt, the CPU must read the frame
(accessing an MB in the 0x80 address) and then clear the interrupt. The act of clearing the interrupt triggers
the FIFO engine to replace the MB in 0x80 with the next frame in the queue, and then issue another
interrupt to the CPU. If the FIFO is full and more frames continue to be received, an OVERFLOW
interrupt is issued to the CPU and subsequent frames are not accepted until the CPU creates space in the
FIFO by reading one or more frames. A warning interrupt is also generated when 4 frames are accumulated
in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target application, thus
reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8
