Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
25-40
Freescale Semiconductor
Preliminary
After requesting freeze mode, the user must wait for the FRZACK bit to be asserted in CAN
x
_MCR before
executing any other action, otherwise FlexCAN can operate in an unpredictable way. In freeze mode, all
memory mapped registers are accessible.
Exiting freeze mode is done in one of these ways:
•
CPU negates the FRZ bit in the CAN
x
_MCR
•
The MCU exits debug mode and/or the HALT bit is negated
After it is out of freeze mode, FlexCAN tries to resynchronize to the CAN bus by waiting for
11 consecutive recessive bits.
25.4.8.2
Module Disabled Mode
This low-power mode is entered when the CAN
x
_MCR[MDIS] bit is asserted. If the module is disabled
during freeze mode, it shuts down the clocks to the CPI and MBM submodules, sets the
CAN
x
_MCR[MDISACK] bit and negates the CAN
x
_MCR[FRZACK] bit. If the module is disabled
during transmission or reception, FlexCAN does the following:
•
Waits to be in either idle or bus off state, or else waits for the third bit of intermission and then
checks it to be recessive
•
Waits for all internal activities like move in or move out to finish
•
Ignores its Rx input pin and drives its Tx pin as recessive
•
Shuts down the clocks to the CPI and MBM submodules
•
Sets the NOTRDY and MDISACK bits in CAN
x
_MCR
The bus interface unit continues to operate, enabling the CPU to access memory mapped registers except
the free-running timer, the CAN
x
_ECR and the message buffers, which cannot be accessed when the
module is disabled. Exiting from this mode is done by negating the CAN
x
_MCR[MDIS] bit, which will
resume the clocks and negate the CAN
x
_MCR[MDISACK] bit.
25.4.8.3
Stop Mode
This is a system low-power mode in which all MCU clocks are stopped for maximum power savings. If
FlexCAN receives the global stop mode request during freeze mode, it sets the LPM_ACK bit, negates the
FRZ_ACK bit and then sends a stop acknowledge signal to the CPU, in order to shut down the clocks
globally. If stop mode is requested during transmission or reception, FlexCAN does the following:
•
Waits to be in idle or bus off state, or waits for the third bit of intermission and checks it to be
recessive
•
Waits for all internal activities like arbitration, matching, move-in, and move-out to finish
•
Ignores its Rx input pin and drives its Tx pin as recessive
•
Sets the NOT_RDY and LPM_ACK bits in CANx_MCR
•
Sends a stop acknowledge signal to the CPU, so that it can shut down the clocks globally
Exiting stop mode is done by the CPU resuming the clocks and removing the stop mode request.
