Enhanced Modular I/O Subsystem (eMIOS200)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
26-17
Preliminary
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Counter bus selector, which selects the time base to be used by the channel for all timing functions
•
A programmable clock prescaler
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Two double buffered data registers, A and B, that allow up to two input capture and/or output
compare events to occur before software intervention is needed
•
Two comparators (equal only), A and B, which compare the selected counter bus with the value in
the data registers
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Internal counter, which can be used as a local time base or to count input events
•
Programmable input filter, which ensures that only valid pin transitions are received by channel
•
Programmable input edge detector, which detects the rising, falling or either edges
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An output flip-flop, which holds the logic level to be applied to the output pin
•
eMIOS200 status and control register
•
An output disable input selector, which selects the output disable input signal that will be used as
output disable
Figure 26-11. Unified Channel Block Diagram
channel_controller
ipd_done
ipd_req
uc_int_flag
biu_channel_en[n]
biu_a_en
biu_b_en
biu_cnt_en
Clock
Prescaler
biu_control_en
biu_status_en
ips_byte[7:0]
ips_byte[15:8]
ips_byte[23:16]
ips_byte[31:24]
ips_rwb
Programmable
Filter
channel_datapath
Comparator A
Comparator B
uc_cnt_rd_data[n]
uc_cnt_rd_data[n]
emios_counter_bus[0]
emios_counter_bus[1]
Match Logic
Mode Logic
RWCB
RCB
IIB
Counter Bus
Unified Channel
Control Signals
uc_rd_data[31:0]
ips_wdata[31:0]
ips_addr[29:27]
