Enhanced Modular I/O Subsystem (eMIOS200)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
26-33
Preliminary
Figure 26-30. OPWFMB Mode from 100% to 0% Duty Cycle
A 0% duty cycle signal is generated if A1=0 as shown in cycle 9 in
. In this case, the
B1=0x000008 match from cycle 8 occurs at the same time as the A1=0x000000 match from cycle 9. Refer
to
for a description of the A1 and B1 match generation. In this case, the A1 match has
precedence over the B1 match and the output signal transitions to EDPOL.
26.5.1.1.9
Center-Aligned Output PWM Buffered with Dead-Time (OPWMCB) Mode
This operation mode generates a center-aligned PWM with dead-time insertion to the leading or trailing
edge. A1 and B1 registers are double buffered to allow smooth output signal generation when changing
A2 or B2 registers values.
The selected counter bus must be running in up/down counter mode, as shown in
base selected for a channel configured to OPWMCB mode should be a channel configured to MCB mode.
BSL bits select the time base. The time base must start at 0x000001 and upward not prior to OPWMCB
mode is active. Register A1 contains the ideal duty cycle for the PWM signal and is compared with the
selected time base. Register B1 contains the dead-time value and is compared against the internal counter.
For a leading edge dead-time insertion, the output PWM duty cycle is equal to the difference between
register A1 and register B1, and for a trailing edge dead-time insertion, the output PWM duty cycle is equal
to the sum of register A1 and register B1. Mode[6] bit selects between trailing and leading dead-time
insertion, respectively.
NOTE
The internal prescaler of the OPWMCB channel must be set to the same
value of the MCB channel prescaler. These prescalers must also be
synchronized. In this case, A1 and B1 registers represent the same timing
scale for duty cycle and dead-time insertion.
describes the load of A1 and B1 registers, which occurs when the selected counter bus
reaches the value one. This counter value defines the cycle boundary. Values written to A2 or B2 within
cycle (n) are loaded into A1 or B1 registers, respectively, and used to generate matches in cycle (n+1).
0x000008
0x000007
0x000006
0x000005
0x000004
0x000003
0x000002
0x000001 0x000000
0%
100%
EMIOS_CCNTR
EDPOL = 0
A1 Value
B1 Value
Output Pin
0x000008
Prescaler = 1
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
0x000007
0x000006
0x000005
0x000004
0x000003
0x000002
0x000001
0x000000
A2 Value
Time
