Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
27-10
Freescale Semiconductor
Preliminary
27.3.2.5
I
2
C Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to IBDR, a data transfer is initiated. The most significant bit
is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode,
the same functions are available after an address match has occurred. The TX bit in the IBCR must
correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin.
For instance, if the I
2
C is configured for master transmit but a master receive is desired, then reading the
IBDR will not initiate the receive.
Reading the IBDR will return the last byte received while the I
2
C is configured in either master receive or
slave receive modes. The IBDR does not reflect every byte that is transmitted on the I
2
C bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master-transmit mode, the first byte of data written to IBDR following assertion of MS is used for the
address transfer and should comprise the calling address (in position D0–D6) concatenated with the
required R/W bit (in position D7).
bit 4
Reserved for future use. A read will return 0; must be written as 0.
SRW
Slave Read/Write. When IAAS is set, this bit indicates the value of the R/W command bit of the calling address sent
from the master. This bit is valid only when the I-bus is in slave mode, a complete address transfer has occurred with
an address match and no other transfers have been initiated. By programming this bit, the CPU can select slave
transmit/receive mode according to the command of the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
IBIF
I-Bus Interrupt Flag. The IBIF bit is set when one of the following conditions occurs:
• Arbitration lost (IBAL bit set)
• Byte transfer complete (TCF bit set and DMAEN bit not set)
• Addressed as slave (IAAS bit set)
• NoAck from slave (MS & TX bits set)
• I
2
C bus going idle (IBB high-low transition and enabled by BIIE)
A processor interrupt request will be caused if the IBIE bit is set. This bit must be cleared by software, by writing a 1
to it. A write of 0 has no effect on this bit. In DMA mode (DMAEN set), a byte transfer complete condition will not
trigger the setting of IBIF. All other conditions apply.
RXAK
Received Acknowledge. This is the value of SDA during the acknowledge bit of a bus cycle. If the received
acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits
data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.
0 Acknowledge received.
1 No acknowledge received.
Offset: 0x0004
Access: Read/write any time
0
1
2
3
4
5
6
7
R
Data
W
Reset
0
0
0
0
0
0
0
0
Figure 27-8. I
2
C Bus Data I/O Register (IBDR)
Table 27-6. IBSR Field Descriptions (continued)
Field
Description
