Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
27-11
Preliminary
27.3.2.6
I
2
C Bus Interrupt Config Register (IBIC)
27.4
Functional Description
27.4.1
I-Bus Protocol
The I
2
C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open-drain or open-collector outputs. A logical AND function is exercised on
both lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. They are described briefly in the following sections and illustrated in
.
Offset: 0x0005
Access: Read/write any time
0
1
2
3
4
5
6
7
R
BIIE
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 27-9. I
2
C Bus Interrupt Config Register (IBIC)
Table 27-7. IBIC Field Descriptions
Field
Description
BIIE
Bus Idle Interrupt Enable Bit. This config bit can be used to enable the generation of an interrupt after the I
2
C bus
becomes idle. After this bit is set, an IBB high-low transition sets the IBIF bit. This feature can be used to signal to
the CPU the completion of a STOP on the I
2
C bus.
0 Bus idle interrupts disabled.
1 Bus idle interrupts enabled.
bits 1–7
Reserved for future use. A read will return 0; must be written as 0.
