External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-4
Freescale Semiconductor
Preliminary
29.1.3.4
Configurable Bus Speed Modes
In configurable bus speed modes, the external CLKOUT frequency is divided down from the internal
system clock. The EBI behavior remains dictated by the mode of the EBI, except that the EBI drives and
samples signals at the scaled CLKOUT rather than the internal system clock. This mode is selected by
writing the external clock control register in the system integration module (SIU_ECCR). The
configurable bus speed modes support 1/2 or 1/4 speed modes, meaning that the external CLKOUT
frequency is scaled down (by 2 or 4) compared with that of the internal system clock, which is unchanged.
NOTE
Nothing prevents the user from configuring the SIU register to run the EBI
in 1/2 or 1/4 of system clock frequency; however, the user must ensure that
the maximum operating frequency of the EBI (per the electrical
specification) is not exceeded, or unreliable behavior may result. In the
common case of running the system clock at 66 MHz, this means that only
1/4 speed mode is supported, because at 1/2 speed the maximum EBI bus
frequency (25 MHz) would be exceeded.
29.1.3.5
16-Bit Data Bus Mode
The EBI has an internal 32-bit data bus, but the EBI supports a 16-bit data bus mode for MCUs that have
only 16 data bus signals pinned out, or for systems where the use of a different multiplexed function (e.g.
GPIO) is desired on 16 of the 32 data pins. In this mode, AD[16:31] are the only data signals used by the
EBI by default, though the user can change this to use AD[0:15] instead by modifying the D16_31 bit in
the EBI_MCR.
For EBI-mastered accesses, the operation in 16-bit data bus mode (DBM=1, PS=x) is similar to a
chip-select access to a 16-bit port in 32-bit data bus mode (DBM=0, PS=1), except for the case of a
non-chip-select access of exactly 32-bit size.
EBI-mastered non-chip-select accesses of exactly 32-bit size are supported via a two (16-bit) beat burst
for both reads and writes. See
Section 29.4.2.10, “Non-Chip-Select Burst in 16-bit Data Bus Mode
,” for
more details. Non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion.
16-bit data bus mode is entered when DBM=1 in the EBI_MCR. On MPC5510, the default value of the
DBM bit out of reset is 0. Thus the EBI operates in 32-bit data bus mode by default.
29.1.3.6
Multiplexed Address on Data Bus Mode
This mode covers several cases aimed at reducing pin count on MCU and external components. In this
mode, the AD pins will drive (for internal master cycles) the address value on the first clock of the cycle
(while TS is asserted). The AD pins will also be used to sample the incoming address on the first clock of
a cycle for external master accesses. The address latch enable (ALE) is valid when the address is presented
on the AD pins and the falling edge of ALE may be used to capture the valid address.
The memory controller supports per-chip-select selection of multiplexing address/data through the
BRx[AD_MUX] bit.
