External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
29-11
Preliminary
29.3.2.4
EBI Transfer Error Status Register (EBI_TESR)
The EBI_TESR contains a bit for each type of transfer error on the external bus. A bit set to logic 1
indicates what type of transfer error occurred since the last time the bits were cleared. Each bit can be
cleared by reset or by writing a 1 to it. Writing a 0 has no effect.
This register is not writable in module disable mode due to the use of power saving clock modes.
D16_31
Data Bus 16_31 Select. The D16_31 bit controls whether the EBI uses the AD[0:15] or AD[16:31] signals, when
in 16-bit data bus mode (DBM=1) or for chip-select accesses to a 16-bit port (PS=1). For systems using A/D
muxing with a 16-bit port, it is recommended to set D16_31 to 1.
0 AD[0:15] signals are used for 16-bit port accesses
1 AD[16:31] signals are used for 16-bit port accesses
AD_MUX
Address on Data Bus Multiplexing Mode. The AD_MUX bit controls whether non-chip-select accesses have the
address driven on the data bus in the address phase of a cycle.
0 Only data on data pins for non-CS accesses.
1 Address on data multiplexing mode is used for non-CS accesses.
DBM
Data Bus Mode. Controls whether the EBI is in 32-bit or 16-bit data bus mode. On MPC5510, the default value
of DBM is 0.
0 32-bit data bus mode is used.
1 16-bit data bus mode is used.
Offset: 0x0008
Access: User read/write to clear
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEAF BMTF
W
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 29-3. EBI Transfer Error Status Register (EBI_TESR)
Table 29-5. EBI_TESR Field Descriptions
Field
Description
bits 0–29 Reserved.
Table 29-4. EBI_MCR Field Descriptions (continued)
Field
Description
