External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
29-13
Preliminary
29.3.2.6
EBI Base Registers 0–3 (EBI_BRn)
The EBI_BR
n
are used to define the base address and other attributes for the corresponding chip select.
Offset: 0x0010 (EBI_BR0)
0x0018 (EBI_BR1)
0x0020 (EBI_BR2)
0x0028 (EBI_BR3)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
BA
BA
W
Reset
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BA
0
0
0
PS
0
0
0
AD_
MUX
BL
WEBS TBDIP
0
SETA
BI
V
W
Reset
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
Figure 29-5. EBI Base Registers 0–3 (EBI_BRn)
Table 29-7. EBI_BRn Field Descriptions
Field
Description
BA
Base Address. Compared to the corresponding unmasked address signals among ADDR[0:16] of the internal
address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal
bus master.
Note: The upper 3 bits of the BA field, EBI_BRn[0:2] are tied to a fixed value of 001. These bits can be read but
not written. They are ignored by the EBI during the chip-select address comparison
bits 17–19
Reserved.
PS
Port Size. Determines the data bus width of transactions to this chip select bank.
0 32-bit port.
1 16-bit port.
Note: If EBI_MCR[DBM] is set for 16-bit data bus mode, the PS bit value is ignored and is always treated as a 1
(16-bit port).
bits 21–23
Reserved.
AD_MUX
Address on Data Bus Multiplexing. The AD_MUX bit controls whether accesses for this chip select have the
address driven on the data bus in the address phase of a cycle. On MPC5510, the default value of AD_MUX is 1.
0 Address on data multiplexing mode is disabled for this chip select.
1 Address on data multiplexing mode is enabled for this chip select.
