External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-18
Freescale Semiconductor
Preliminary
29.4.1.3
Burst Support (Wrapped Only)
The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular
memory region, clear the burst inhibit (BI) bit in the appropriate base register. All external bursts use a
4-word burst length on MPC5510. See
Section 29.4.2.5, “Burst Transfer
,” for more details.
In 16-bit data bus mode (EBI_MCR[DBM]=1), a special 2-beat burst case is supported for reads and writes
for 32-bit non-chip select accesses only. This allows 32-bit coherent accesses to another MCU. See
Section 29.4.2.10, “Non-Chip-Select Burst in 16-bit Data Bus Mode
Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides
the special case of 32-bit accesses in 16-bit data bus mode.
Burst writes are not supported for any other case besides the special case of 32-bit non-chip select writes
in 16-bit data bus mode. Internal requests to write more than 32 bits (such as a cache line) externally are
broken up into separate 32-bit or 16-bit external transactions according to the port size. See
Section 29.4.2.6, “Small Accesses (Small Port Size and Short Burst Length)
cases.
29.4.1.4
Bus Monitor
When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is
received within a maximum timeout period for non-chip select accesses (that is, accesses that use external
TA). The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR. Each time a timeout
error occurs, the BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus
(CLKOUT) cycles. Thus the effective real-time period is multiplied (by 2, 3, etc) when a slower-speed
mode is used, even though the BMT field itself is unchanged.
29.4.1.5
Port Size Configuration Per Chip Select (16 or 32 Bits)
The EBI supports memories with data widths of 16 or 32 bits. The port size for a particular chip select is
configured by writing the PS bit in the corresponding base register.
29.4.1.6
Configurable Wait States
From 0 to 15 wait states can be programmed for any cycle that the memory controller generates, via the
SCY bits in the appropriate option register. From zero to three wait states between burst beats can be
programmed using the BSCY bits in the appropriate option register.
29.4.1.7
Configurable Internal or External TA per chip select
Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or
externally (by an external device). See
Section 29.3.2.6, “EBI Base Registers 0–3 (EBI_BRn)
,” for more
details on SETA bit usage.
