External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
29-49
Preliminary
29.5.3.1
Example Wait State Calculation
This example applies to any chip-select memory, synchronous or asynchronous.
For example, if there is a memory with 50 ns access time, and the external bus is running at 66 MHz
(CLKOUT period: 15.2 ns). Assume the input data spec for the MCU is 4 ns.
number of wait states = (access time) / (CLKOUT period) + (0 or 1) (depending on set-up time)
50/15.2 = 3 with 4.4 ns remaining (at least three wait states are needed, now check set-up time)
15.2-4.4=10.8ns (this is the achieved input data set-up time)
Because actual input setup (10.8 ns) is greater than the input setup spec (4.0 ns), three wait states is
sufficient. If the actual input setup was less than 4.0 ns, four wait states would be used instead.
29.5.3.2
Timing and Connections for Asynchronous Memories
The connections to an asynchronous memory are the same as for a synchronous memory, except that the
CLKOUT, TS, and BDIP signals are not used.
shows a block diagram of an MCU connected
to an asynchronous memory.
Figure 29-36. MCU Connected to Asynchronous Memory
shows a timing diagram of a read operation to a 16-bit asynchronous memory using three
shows a timing diagram of a write operation to a 16-bit asynchronous memory
using three wait states.
Flash memories typically use one WE signal as shown, RAMs use two or four (16-bit or 32-bit).
*
WE0
ADDR[9:30]
DATA[0:15]
OE
MCU
WE*
A[0:21]
D[0:15]
OE
Asynchronous
Memory
CS0
CE
CAL_CS0
