FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
30-5
Preliminary
•
Two independent receive FIFOs
— One receive FIFO per channel
— Up to 255 entries for each FIFO
— Global frame ID filtering, based on both value/mask filters and range filters
— Global channel ID filtering
— Global message ID filtering for the dynamic segment
•
Four configurable slot error counters
•
Four dedicated slot status indicators
— Used to observe slots without using receive message buffers
•
Measured value indicators for the clock synchronization
— Internal synchronization frame ID and synchronization frame measurement tables can be
copied into the FlexRay Memory
•
Fractional macroticks are supported for clock correction
•
Maskable interrupt sources provided via individual and combined interrupt lines
•
One absolute timer
•
One timer that can be configured to absolute or relative
30.1.6
Modes of Operation
This section describes the basic operational power modes of the FlexRay block.
30.1.6.1
Disabled Mode
This is the mode the FlexRay block enters during hard reset. The FlexRay block indicates that it is in the
disabled mode by negating the module enable bit MEN in the
Module Configuration Register (MCR)
No communication is performed on the FlexRay bus.
All registers with the write access conditions
Any Time
and
Disabled Mode
can be accessed for writing as
stated in
Section 30.5.2, “Register Descriptions”
.
The application configures the FlexRay block by accessing the configuration bits and fields in the
30.1.6.1.1
Leave Disabled Mode
The FlexRay block leaves the disabled mode and enters the normal mode, when the application writes 1
to the module enable bit MEN in the
Module Configuration Register (MCR)
NOTE
When the FlexRay block was enabled, it cannot be disabled the later on.
