FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
30-7
Preliminary
30.2.1.2
FR_A_TX — Transmit Data Channel A
The FR_A_TX signal carries the transmit data for channel A to the corresponding FlexRay bus driver.
30.2.1.3
FR_A_TX_EN — Transmit Enable Channel A
The FR_A_TX_EN signal indicates to the FlexRay bus driver that the FlexRay block is attempting to
transmit data on channel A.
30.2.1.4
FR_B_RX — Receive Data Channel B
The FR_B_RX signal carries the receive data for channel B from the corresponding FlexRay bus driver.
30.2.1.5
FR_B_TX — Transmit Data Channel B
The FR_B_TX signal carries the transmit data for channel B to the corresponding FlexRay bus driver
30.2.1.6
FR_B_TX_EN — Transmit Enable Channel B
The FR_B_TX_EN signal indicates to the FlexRay bus driver that the FlexRay block is attempting to
transmit data on channel B.
30.2.1.7
FR_DBG[3], FR_DBG[2], FR_DBG[1], FR_DBG[0] — Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe signal selection
refer to
Section 30.6.16, “Strobe Signal Support.”
30.3
Controller Host Interface Clocking
The clock for the CHI is derived from the system bus clock and has the same phase and frequency. Because
the FlexRay protocol requires data delivery at fixed points in time, the memory read cycles from the FRM
must be finished after a fixed amount of time. To ensure this, a minimum frequency f
chi
of the CHI clock
is required, which is given in
Eqn. 30-1
Additional requirements for the minimum frequency of the CHI clock result from the number of message
buffer. The requirement is provides in
Section 30.7.3, “Number of Usable Message Buffers
30.4
Protocol Engine Clocking
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal
oscillator and the second source is an internal PLL
1
. The clock source to be used is selected by the clock
source select bit CLKSEL in the
Module Configuration Register (MCR)
.
1. Due to the tight timing requirements and overall system requirements of FlexRAY systems, usage of the PLL as the clock
source has not been fully evaluated. It is recommended to use a 40 MHz crystal for the clock source.
f
chi
32MHz
≥
