FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
30-15
Preliminary
30.5.2.5
System Memory Base Address High Register (SYMBADHR) and
System Memory Base Address Low Register (SYMBADLR)
Single Channel Device Mode
1
0
0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN not driven by FlexRay block
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by FlexRay block
PE channel 0 idle
PE channel 1 idle
0
1
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by FlexRay block
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by FlexRay block
PE channel 0 active
PE channel 1 idle
1
0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by FlexRay block
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by FlexRay block
PE channel 0 active, uses cCrcInit[B] (see
)
PE channel 1 idle
1
1
reserved
Table 30-10. FlexRay Channel Bit Rate Selection
MCR[BITRATE]
FlexRay Channel Bit Rate [Mbit/s]
000
10.0
001
5.0
010
2.5
011
8.0
100
reserved
101
reserved
110
reserved
111
reserved
Base + 0x0004
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SYS_MEM_BASE_ADDR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-4. System Memory Base Address High Register (SYMBADHR)
Base + 0x0006
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SYS_MEM_BASE_ADDR[15:4]
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-5. System Memory Base Address Low Register (SYMBADLR)
Table 30-9. FlexRay Channel Selection (Sheet 2 of 2)
SCM
CHB
CHA
Description
