System Clock Description
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
3-5
Preliminary
3.4
Clock Dividers
3.4.1
System Clock Select
The source for the system clock can be selected by the SYSCLKSEL field of the SIU system clock register
(SIU_SYSCLK) to be the 16 MHz IRC, the XOSC, or the PLL.
3.4.2
System Clock Dividers
The system clock dividers can be programmed to create a system clock, which is created from the selected
clock source divided by 1, 2, 4, or 8, based on the setting of the SYSCLKDIV field in the SIU system clock
register (SIU_SYSCLK).
3.4.3
External Bus Clock (CLKOUT) Divider
The external bus clock (CLKOUT) divider can be programmed to create a CLKOUT, which is created
from the system clock divided by 1, 2, or 4, based on the settings of the EBDF bit field in the SIU external
clock control register (SIU_ECCR). The reset value of EBDF selects a CLKOUT frequency of one half of
the system clock frequency. The EBI supports gating of the CLKOUT signal when there are no external
bus accesses in progress.
The CLKOUT divider provides a nominal 50% duty cycle clock. There is no guaranteed phase relationship
between CLKOUT and MCKO.
3.4.4
Nexus Message Clock (MCKO) Divider
The Nexus message clock (MCKO) divider can be programmed to divide the system clock by one, two,
four, or eight based on the MCKO_DIV bit field in the port configuration register (PCR) in the Nexus port
controller (NPC). The reset value of MCKO_DIV selects an MCKO clock frequency one half of the
system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port.
The MCKO_EN bit may be used to disable the MCKO clock. The MCKO_GT bit may be used to disable
the MCKO clock when Nexus is not actively transmitting messages on the Nexus port.
The MCKO divider provides a nominal 50% duty cycle clock. There is no guaranteed phase relationship
between CLKOUT and MCKO.
3.4.5
Peripheral Clock Dividers
The peripheral clock dividers provide a mechanism to reduce run power when it is not necessary to clock
peripherals at the full system clock frequency.
