Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-5
Preliminary
4.3.2.2
FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
This is one of two FMPLL synthesizer control registers that are used to access enhanced features in the
FMPLL. The bit fields in the ESYNCR1 behave as described in
.
LOCK
PLL Lock Status Bit. The LOCK bit indicates whether the PLL has acquired lock. PLL lock occurs when the
synthesized frequency matches to within approximately 0.75% of the programmed frequency. The PLL loses lock
when a frequency deviation of greater than approximately 1.5% occurs. If the LOCK bit is read when the PLL
simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the PLL.
If operating in PLL Off mode, LOCK remains cleared after reset.
1 PLL is locked
0 PLL is unlocked
LOCF
Loss-of-Clock Flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to the bit. Writing 0 has
no effect. Asserting reset will clear the flag. If clocks return to normal after the flag has been set, the bit will remain
set until cleared by either writing 1 or asserting reset. A loss-of-clock condition can only be detected if LOCEN=1.
1 Interrupt service requested
0 Interrupt service not requested
CALDONE
Calibration Complete. The CALDONE bit is an indication of whether the calibration sequence has been
completed since the last time modulation was enabled. If CALDONE=0 then the calibration sequence is in
progress or modulation is disabled. If CALDONE=1 then the calibration sequence has been completed, and
frequency modulation is operating.
1 Calibration complete
0 Calibration not complete
CALPASS
Calibration Passed. The CALPASS bit tells whether the calibration routine was successful. If CALPASS=1 and
CALDONE=1 then the routine was successful. If CALPASS=0 and CALDONE=1, then the routine was
unsuccessful. When the calibration routine is initiated the CALPASS is asserted. CALPASS remains asserted
until modulation is disabled by clearing the EDEPTH bits in the ESYNCR2 register or a failure occurs within the
FMPLL calibration sequence.
1 Calibration successful
0 Calibration unsuccessful
If calibration is unsuccessful, then actual depth is not guaranteed to match the desired depth
Table 4-3. System Clock Status Per Mode
MODE
PLLSEL
PLLREF
Clock Mode
0
X
X
PLL Off mode
1
0
0
Reserved
1
1
0
Normal PLL mode with external clock reference
1
1
1
Normal PLL mode with crystal clock reference
Table 4-2. SYNSR Register Field Descriptions (continued)
Field
Description
