FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
30-123
Preliminary
Figure 30-130. Message Buffer Reconfiguration Scheme
30.6.9
Receive FIFO
This section provides a detailed description of the two receive FIFOs.
30.6.9.1
Overview
The receive FIFOs implement the queued receive buffer defined by the
Protocol Specification, Version 2.1 Rev A.
One receive FIFO is assigned to channel A, the other receive
FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in
Section 30.6.3.3, “Receive FIFO”.
The area in
the FRM for each of the two receive FIFOs is characterized by:
•
The index of the first FIFO entry given by
Receive FIFO Start Index Register (RFSIR)
•
The number of FIFO entries and the length of each FIFO entry as given by
30.6.9.2
Receive FIFO Configuration
The receive FIFO control and configuration data are given in
Section 30.6.3.7, “Receive FIFO Control and
The configuration of the receive FIFOs consists of two steps.
The first step is the allocation of the required amount of FRM for the FlexRay window. This includes the
allocation of the message buffer header area and the allocation of the message buffer data fields. For more
details see
Section 30.6.4, “FlexRay Memory Layout”.
The second step is the programming of the configuration data register while the PE is in
POC:config.
The following steps configure the layout of the FIFO.
•
The number of the first message buffer header index that belongs to the FIFO is written into the
Receive FIFO Start Index Register (RFSIR)
•
The depth of the FIFO is written into the FIFO_DEPTH field in the
.
•
The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in
the
Receive FIFO Depth and Size Register (RFDSR)
.
single RX
single TX
double TX (commit side)
double TX (transmit side)
RC1
RC1
RC1
RC2
RC3
RC3
