Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-7
Preliminary
bits 16–23
Reserved.
EMFD
Enhanced Multiplication Factor Divider. The EMFD bits control the value of the divider in the PLL feedback
loop. The value specified by the EMFD bits establish the multiplication factor applied to the reference
frequency. The decimal equivalent of the EMFD binary number is substituted into the equation from
for F
sys
to determine the equivalent multiplication factor. The range of settings is
32
≤
EMFD
≤
132.
Note: EMFD values less than 32 and greater than 132 are invalid and will cause the PLL to produce an
unpredictable clock output. The VCO frequency must be within the f
vco
specification (see MPC5510
data sheet)
When the EMFD bits are changed, the PLL loses lock.If the EMFD bits are changed during FM calibration,
the current calibration sequence is terminated and the DEPTH bits are cleared. The PLL will re-lock to the
new EMFD value you must manually re-enable modulation. To prevent an immediate reset, clear the LOLRE
bit before writing the EMFD bits.
In PLL Off mode the EMFD bits have no affect.
shows the available divide ratios.
Table 4-5. Enhanced Pre-divider Ratios
EPREDIV
Input Divide Ratio (1)
0000
1
0001
2 (default for MPC5510)
0010
3
0011
4
0100
5
0101
6
0110
Invalid
0111
8
1000
Invalid
1001
10
1010–1111
Invalid
Table 4-6. Enhanced Feedback Divide Ratios
EMFD
Feedback Divide Ratio (EMFD+16)
0000_0000–0001_1111
Invalid
0010_0000
48
0010_0001
49
0010_0010
50
0010_0011
51
0010_0100
52
Table 4-4. ESYNCR1 Register Field Descriptions (continued)
Field
Description
