Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
4-8
Freescale Semiconductor
Preliminary
4.3.2.3
FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
This is the second of two enhanced versions of the FMPLL synthesizer control register used to access
enhanced features in the FMPLL. The bit fields in the ESYNCR2 behave as described in
.
0010_0101
53
.
.
0101_0011
.
.
.
.
99 (default for MPC5510)
.
.
1000_0100
148
1000_0101–1111_1111
Invalid
FMOffset: PLL_BAS 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
LOCEN LOLRE LOCRE
LOL
IRQ
LOC
IRQ
0
ERATE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
EDEPTH
0
0
ERFD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Figure 4-4. FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
Table 4-7. ESYNCR2 Field Descriptions
Field
Description
bits 0–7
Reserved.
LOCEN
Loss-of-Clock Enable. The LOCEN bit determines whether the loss-of-clock function is operational along with
backup clock modes, and interrupt and reset functions. See
Section 4.4.3.2, “Loss-of-Clock Detection,”
for
more information.
In PLL Off mode, this bit has no affect.
LOCEN does not affect the loss-of-lock circuitry.
1 Loss-of-clock enabled.
0 Loss-of-clock disabled.
LOLRE
Loss-of-Lock Reset Enable. The LOLRE bit determines how the integration module handles a loss-of-lock
indication. See
Section 4.4.3.1, “PLL Lock Detection,”
for more information.
When operating in normal PLL mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset
is immediately asserted.
The LOLRE bit has no affect in PLL Off mode.
1 Assert reset on loss of lock enabled.
0 Assert reset on loss of lock disabled.
Table 4-6. Enhanced Feedback Divide Ratios
EMFD
Feedback Divide Ratio (EMFD+16)
