Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
31-3
Preliminary
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Formats and calibrates conversion result data coming from the on-chip ADC.
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Generates the internal multiplexer control signals and the select signals used by the external
multiplexers.
also depicts data flow through the eQADC. Commands are contained in system memory in an
user defined data structure. The most likely data structure to be used is a queue as depicted in the
1
. Command data is moved from the command queue (CQueue) to the CFIFOs by either the
host CPU or by the DMAC. After a CFIFO is triggered and becomes the highest priority CFIFO using a
certain CBuffer, command data is transferred from the CFIFO to the ADC on chip. The ADC executes the
command, and the result is moved through the result format and calibration sub-block to the RFIFO
specified by a field in the command that initiated the conversion. When data is stored in an RFIFO, data
is moved from the RFIFO by the host CPU or by the DMAC to a data structure in system memory depicted
in the
as a result queue (RQueue).
31.1.2
Features
The eQADC has these major features:
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One on-chip RSD cyclic ADC
— 12-bit AD resolution
— Targets up to 9-bit accuracy at 400 KSample/s (ADC_CLK=6 MHz) (the actual accuracy is
TBD, subject to the final characterization)
— Single-ended signal range from 0 to 5 V
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
— Provides time stamp information when requested
— Parallel interface to eQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
— The REFBYPC is a stable reference voltage for the eQADC and is used to connect a 100 nF
bypass capacitor between the REFBYPC pin and VRL.
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Automatic application of ADC calibration constants
— Provision of reference voltages (25% VREF
2
and 75% VREF) for ADC calibration purposes
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40 input channels available to the on-chip ADC
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Priority-based CFIFOs
— Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority.
When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority
CFIFO is always served first.
— Supports software and several hardware trigger modes to arm a particular CFIFO
— Generates interrupt when command coherency is not achieved
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External hardware triggers
1. Command and result data can be stored in system memory in any user defined data structure. However, in this document it
will be assumed that the data structure of choice is a queue, since it is the most likely data structure to be used and because
queues are the only type of data structure supported by the DMAC.
2. VREF=VRH–VRL.
